Low voltages are widely used in industry to reduce power, and most modern semiconductor devices are designed to operate on low voltages. However, many semiconductor devices are used in systems where higher voltages are used as inputs, outputs, etc. Microcontroller applications often interface to devices at different voltages, and high impedance interfaces are often required for low power applications and high integrity interface levels. In practice, many semiconductor devices need to be able to handle input voltages that exceed the supply voltage of the device. It is a challenge for a designer to make the device capable of tolerating such over voltages at an input pin without drawing any direct (DC) current from the external driving source. Tolerating over voltages (i.e. input voltages that exceed the device supply voltage) typically involves allowing wells to float up with the over-voltage signal. PMOS (P-type Metal Oxide Semiconductor) devices may have their nwell (body/bulk) connected in a “floating” configuration which keeps it at the device supply voltage during normal operation, but when an input exceeds the supply voltage, the nwell voltage rises with that input voltage. In this way, PMOS devices connected to the pad can avoid having their well-diodes forward biased, which would load the pad in an undesirable way. However, in order to accomplish this, some amount of DC current is typically drawn from the over-voltage source as long as it persists at voltages exceeding the device supply voltage. This input current load is often undesirable, and may not be tolerable in some applications.
FIG. 1 shows a conventional input circuit 10 having a load current. The conventional input circuit 10 has the pad 12 coupled to a Nwell bias circuit 14. The Nwell bias circuit 14 has an output (Nwell Bias) that is coupled to the body of the p-type transistor 16. The source 18 of the transistor 16 is coupled to the supply voltage 20. The drain 22 of the transistor 16 is coupled to the pad 12 and to the drain 24 of n-type transistor 26. The source 28 of the transistor 26 is coupled to ground 30. The pad 12 is coupled to a buffer circuit 32. FIG. 2 shows a detailed version of the conventional input circuit 10. In FIG. 2, devices 40, 42, 44 provide the DC current path during over-voltage. These are used to control the voltage of the body of transistor 16, which determines whether the Nwell bias signal will be set to the device supply or allowed to float up with the pad's over voltage (through transistor 46). The weak discharge devices, transistors 42, 44, allow the over-voltage (overv) signal 48 to return low once the over-voltage is removed.
It would be desirable to have an input circuit having low or zero DC load current.